As the resolution of display devices increases, so does the amount of display data, which increases exponentially. This increase in display data generally translates to an increase in the storage and physical size of the frame buffer memory of a display device. For example, a Quad High Definition (QHD) display having an 11 MB SRAM frame buffer may occupy an area of roughly 88 mm2 when fabricated using 65 nm process technology.
Display data compression may be used to significantly reduce the size required of the frame buffer, resulting in major cost and power savings. A 2:1 compression rate is recently being used for production display devices, and the Video Electronics Standards Association (VESA) is trying to push the compression rate up to 4:1. Although compression rates higher than 4:1 may be possible, resulting compression errors may generate visual artifacts for certain images.
Accordingly, in view of the foregoing, there exists a need for a system and method of compensating for image compression errors to improve the image quality of the displayed images.